Patricia Highsmith: “Oh time, though art strange.”
We imagined, in the past, this future of ours in semiconductor device manufacturing but, despite our pooled imagination, and despite our best efforts, we just couldn’t make that envisioned future a here-and-now reality then using the machines and processes we had at the time.
However, in a fortuitous and virtuous cycle, advances in transistor architectures and advances in our ability to build those architectures at scale have been one long continuous improvement arc, an arc spanning the course of at least four decades. To the point today where smart machines, looking over our shoulders as assistants, or being let loose to toil away on thorny problems without too much supervision, design the machines that manufacture the machines, silicon chips, that are the basis for our world.
I am talking about the span that runs from the 29,000 transistors comprising an Intel 8088 microprocessor, which is where I entered the semiconductor industry, to the Cerebras Wafer Scale Engine of today, said to contain 2.6 trillion transistors, 850,000 AI-optimized cores, and 40 gigabytes of high performance on-wafer memory. Big Iron.
I am talking about System-On-a-Chip (SoC) processors, built on 5-nanometer manufacturing technology, with 33.7 billion transistors, 10-core CPUs, and 16-core GPUs.
In your laptop.
And you may ask yourself, “Well, how did we get here?” Computational lithography is one part of the answer. According to ASML, “Without computational lithography, it would be impossible for chipmakers to manufacture the latest technology nodes.” At and below the 130nm process node, the (compute-intense) algorithmic models on which computational lithography depends optimize the photomask design “by intentionally deforming the patterns to compensate for the physical and chemical effects that occur during lithography and patterning. The net result: we end up with an accurate replica of the desired chip patterns on the wafer.”